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FMP1617CCX cmos lpram revision 0.1 jun. 2006 1 document title 1m x 16 bit super low power and low voltage full cmos ram revision history preliminary jun.01 st , 2006 revised p/n according to the new p/n system 0.1 preliminary apr. 19 th , 2006 initial draft 0.0 remark draft date history revision no.
FMP1617CCX cmos lpram revision 0.1 jun. 2006 2 1m x 16 bit super low power and low voltage full cmos ram pin description 1 2 3 4 5 6 a b c d e f g h /lb /oe a0 a1 a2 i/o9 /ub a3 a4 /cs i/o10 i/o11 a5 a6 i/o2 vss i/o12 a17 a7 i/o4 vccq i/o13 dnu a16 i/o5 i/o15 i/o14 a14 a15 i/o6 i/o16 a19 a12 a13 we a18a8a9a10a11 /zz i/o1 i/o3 vcc vss i/o7 i/o8 nc 48-fbga : top view(ball down) core power vcc low power modes /zz do not use dnu data inputs/outputs i/o1~i/o16 lower byte(i/o 1~8) /lb address inputs a0~a19 upper byte(i/o9~16) /ub write enable input /we ground vss output enable input /oe i/o power vccq chip select input /cs function name function name functional block diagram precharge circuit. clk gen. vcc vss memory array row addresses i/o circuit column select data cont data cont column addresses data cont control logic /cs /oe /we /ub /lb /zz i/o9~i/o16 i/o1~i/o8 row select features ? process technology : full cmos ? organization : 1m x 16 ? power supply voltage : 1.7~1.95v ? low power & page modes fmp1617cc1 : support the pasr/dpd function fmp1617cc2 : support the direct dpd function fmp1617cc4 : support the pasr/dpd/page function fmp1617cc5 : support the direct dpd/page function ? operating temperature ranges: special (-10?c to +60?c) commercial (0?c to +70?c) extended (-25?c to +85?c) industrial (-40?c to +85?c) ? three state output and ttl compatible ? package type : 48-fbga-6.00x8.00 mm 2 FMP1617CCX- f xxx : normal FMP1617CCX- g xxx : pb-free FMP1617CCX- h xxx : pb-free & halogen free ? separated i/o power(vccq) & core power(vcc) ? page read/write operation by 16 words (fmp1617cc4, fmp1617cc5) ? dpd mode by using mrs only (fmp1617cc1, fmp1617cc4) ? direct dpd mode when /zz goes low (fmp1617cc2, fmp1617cc5) product family isb1 (cmos standby current) icc2 icc1 max. typ. 20ma max. typ. max. typ. min. 100ua 1.8 typ. max. 70ua 15ma 12ma 3ma 1.5ma 70ns 85ns 1.95 1.7 FMP1617CCX- g 70 e FMP1617CCX- g 85 e operating voltage (v) f = fmax f = 1mhz power dissipation speed product family 1. typical values are included for reference only and are not guaranteed or tested. typical values are measured at vcc = vcc ( typ) and t a = 25c. 2. f =fbga, g =fbga(pb-free), h =fbga(pb-free & halogen free), w =wafer 3. operating temperature range: s (-10?c~60?c), c (0?c~70?c), e (-25?c~85?c), i (-40?c~85?c)
FMP1617CCX cmos lpram revision 0.1 jun. 2006 3 product list 48-fbga, 70ns, vcc=1.8v, vccq=1.8v 48-fbga, 85ns, vcc=1.8v, vccq=1.8v FMP1617CCX- g 70 e FMP1617CCX- g 85 e function part name absolute maximum ratings 1) ?c -65 to 150 t stg storage temperature w 1.0 p d power dissipation v -0.2 to 3.6 vcc voltage on vcc supply relative to vss v -0.2 to vcc+0.3v v in , v out voltage on any pin relative to vss unit ratings symbol item 1. stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. functional ope ration should be restricted to recommended operating condition. exposure to absolute maximum rating conditions for extended periods may affect reliability. recommended dc operating conditions -0.2 2) 0.8vccq 0 1.7 1.7 min fmp1617cc 0.2vccq vcc+0.2 1) 0 1.95 1.95 max v v cc supply voltage v v il input low voltage v v ih input high voltage v v ss ground v v ccq i/o operating voltage (vccq vcc) unit symbol item note : 1. overshoot : vcc+1.0v in case of pulse width 20ns. 2. undershoot : -1.0v in case of pulse width 20ns. 3. overshoot and undershoot are sampled, not 100% tested. functional description direct dpd 2) deselected high-z high-z x 1) x 1) x 1) x 1) l x 1) active word write din din l l active upper byte write din high-z l h active lower byte write high-z din h l l x 1) active word read dout dout l l active upper byte read dout high-z l h active lower byte read high-z dout h l h l h l active output disabled high-z high-z l x 1) h h h active output disabled high-z high-z x 1) l h h h l standby deselected high-z high-z h h x 1) x 1) h x 1) low power modes 3) deselected high-z high-z x 1) x 1) x 1) x 1) l h standby deselected high-z high-z x 1) x 1) x 1) x 1) h h power mode i/o9-16 i/o1-8 /ub /lb /we /oe /zz /cs 1. x means don?t care.(must be low or high state) 2. in case of fmp1617cc2 & fmp1617cc5 product 3. in case of fmp1617cc1 & fmp1617cc4 product 1. f =fbga, g =fbga(pb-free), h =fbga(pb-free & halogen free), w =wafer 2. operating temperature range: s (-10?c~60?c), c (0?c~70?c), e (-25?c~85?c), i (-40?c~85?c)
FMP1617CCX cmos lpram revision 0.1 jun. 2006 4 dc and operating characteristics 1. capacitance is sampled, not 100% tested. capacitance 1) (f=1mhz , t a =25?c) 8 8 max - - min pf v io =0v c io input/output capacitance pf v in =0v c in input capacitance unit test condition symbol item ua 10 - - /zz 0.2v, other inputs=0~v cc , no refresh(dpd) i sb0 low power modes ua 70 - - /zz 0.2v, other inputs=0~v cc , ? refresh area selection i sb0a ua 80 - - /zz 0.2v, other inputs=0~v cc , ? refresh area selection i sb0b ua 100 - - /cs v cc -0.2v, /zz v cc -0.2v, other inputs=0~v cc i sb1 standby current(cmos) ua 1 - -1 /cs=v ih , /zz=v ih , /oe=v ih or /we=v il , v io =v ss to v cc i lo output leakage current ua 1 - -1 v in =v ss to v cc i li input leakage current ma 3 - - cycle time=1us, 100%duty, i io =0ma, /cs 0.2v, /zz=v ih , v in 0.2v or v in v cc -0.2v i cc1 average operating current v 0.2vccq i ol =0.5ma v ol output low voltage ma 20 - - cycle time=min, i io =0ma, 100% duty, /cs=v il , /zz=v ih , v in =v il or v ih i cc2 v 0.8vccq i oh =-0.5ma v oh output high voltage 100 0.3 max - - typ - - min ua /zz 0.2v, other inputs=0~v cc , all refresh area selection i sb0c ma /cs=v ih , /zz=v ih , other inputs=v ih or v il i sb standby current(ttl) unit test conditions symbol item -10 to +60 special FMP1617CCX-xxxs 0 to +70 commercial FMP1617CCX-xxxc -25 to +85 extended FMP1617CCX-xxxe 1.7v to 1.95v 1.7v to 1.95v -40 to +85 industrial FMP1617CCX-xxxi v ddq v dd ambient temperature range device operating range
FMP1617CCX cmos lpram revision 0.1 jun. 2006 5 ac operating conditions test conditions (test load and input/output reference) input pulse level : 0.2 to vcc-0.2v input rising and falling time : 5ns input and output reference voltage : 0.5*vccq output load(see right) : c l =30pf+1ttl ac characteristics (v cc =1.7v~1.95v) 30pf 1ttl ns 20k - 20k - tmrc maximum cycle time page ns - 10 - 10 tcp ns 30 - 25 - tpaa page mode address access time ns - 30 - 25 tpc page mode cycle time /cs high pulse width ns - 5 - 5 tow end write to output low-z ns - 0 - 0 tdh data hold from write time ns - 20 - 20 tdw data to write time overlap ns 5 0 5 0 twhz write to output high-z ns - 0 - 0 twr write recovery time ns - 60 - 50 twp write pulse width ns - 70 - 60 tbw /ub, /lb valid to end of write ns - 70 - 60 taw address valid to end of write ns - 0 - 0 tas address set-up time ns - 70 - 60 tcw chip select to end of write ns 20k 85 20k 70 twc write cycle time write ns - 5 - 5 toh output hold from address change ns 5 0 5 0 tohz output disable to high- z output ns 5 0 5 0 tbhz /ub, /lb disable to high- z output ns 5 0 5 0 thz chip disable to high- z output ns - 5 - 5 tolz output enable to low-z output 85ns ns - 10 - 10 tblz /ub, /lb enable to low-z output ns - 10 - 10 tlz chip select to low-z output ns 85 - 70 - tba /ub, /lb access time ns 30 - 25 - toe output enable to valid output ns 85 - 70 - tco chip select to output ns 85 - 70 - taa address access time ns 20k 85 20k 70 trc read cycle time read max min max min 70ns units speed bins symbol parameter list 1. /cs high pulse width is defined by /cs or (/ub and /lb) because /ub & /lb can make standby mode when /ub=high and /lb=high.
FMP1617CCX cmos lpram revision 0.1 jun. 2006 6 power up sequence 1. apply power 2. maintain stable power for a minimum of 200us with /cs=v ih standby mode state machines standby mode characteristics 0 70 (isb0a) ? valid 0 80 (isb0b) ? valid 200 10 (isb0) invalid low power modes 0 100 (isb0c) valid 0 100 (isb1) valid standby mode memory cell data wait time(us) standby current(ua) initial state standby mode active mode low power modes 1 (16m/8m/4m bits) power on /cs=v il /zz=v ih /cs=v ih (or/and /ub=/lb=v ih ) /zz=v ih /cs=v ih /cs=v ih , /zz=v il /cs=v il , /zz=v ih /ub or/and /lb=v il low power modes 2 (data invalid) wait 200us /cs=v ih , /zz=v il /cs=v ih , /zz=v il /cs=v ih /zz=v il /cs=v il /zz=v ih /cs=v ih , /zz=v ih
FMP1617CCX cmos lpram revision 0.1 jun. 2006 7 read cycle (2) (/zz=/we=v ih ) 1. thz and tohz are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. at any given temperature and voltage condition, thz(max.) is less than tlz(min.) both for a given device and from device to device interconnection. 3. do not access device with cycle timing shorter than trc(twc) for continuous periods > 20us. address taa tco tba toe toh tolz tblz tlz data valid high-z thz tbhz tohz /cs /ub, /lb /oe data out trc read cycle (1) (address controlled,/cs=/oe=v il , /zz=/we=v ih , /ub or/and /lb=v il ) address data out trc previous data valid data valid taa toh 1. thz and tohz are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. at any given temperature and voltage condition, thz(max.) is less than tlz(min.) both for a given device and from device to device interconnection. 3. do not access device with cycle timing shorter than trc(twc) for continuous periods > 20us. 4. in case page address skew is over 3ns, tpaa will be out of spec. page read cycle (/zz=/we=v ih , 16 words access) a0~a3 taa tco tba toe high-z thz tbhz tohz /cs /ub, /lb /oe data out trc a4~a20 toh tpc tpc tpc tpc tpc tpc tpc tpaa tpaa tpaa tpaa tpaa tpaa tpaa tlz tblz tolz data valid data valid data valid data valid data valid data valid data valid data valid tmrc
FMP1617CCX cmos lpram revision 0.1 jun. 2006 8 write cycle (2) (/cs controlled, /zz=/we=v ih ) address /cs /ub, /lb /we data out twc twr(4) tbw twp(1) high-z high-z data valid tdw tdh data in tcw(2) tas(3) taw write cycle (3) (/ub, /lb controlled, /zz=v ih ) 1. a write occurs during the overlap (twp) of low /cs and /we. a write begins when /cs goes low and /we goes low with asserting /ub or /lb for single byte operation or simultaneously asserting /ub and /lb for double byte operation. a write ends at the earliest transition when /cs goes high and we goes high. the twp is measured from the beginning of write to the end of write. 2. tcw is measured from the /cs going low to end of write. 3. tas is measured from the address valid to the beginning of write. 4. twr is measured from the end of write to the address change. twr applied in case a write ends as /cs or /we going high. 5. do not access device with cycle timing shorter than trc(twc) for continuous periods > 20us. address /cs /ub, /lb /we data out twc twr(4) tbw twp(1) high-z high-z data valid tdw tdh data in tcw(2) taw tas(3) write cycle (1) (/we controlled, /zz=v ih ) address /cs /ub, /lb /we data out twc tcw(2) twr(4) taw tbw twp(1) tas(3) high-z high-z data undefined data valid tdw tdh tow twhz data in
FMP1617CCX cmos lpram revision 0.1 jun. 2006 9 1. a write occurs during the overlap (twp) of low /cs and /we. a write begins when /cs goes low and /we goes low with asserting /ub or /lb for single byte operation or simultaneously asserting /ub and /lb for double byte operation. a write ends at the earliest transition when /cs goes high and /we goes high. the twp is measured from the beginning of write to the end of write. 2. tcw is measured from the /cs going low to end of write. 3. tas is measured from the address valid to the beginning of write. 4. twr is measured from the end of write to the address change. twr applied in case a write ends as /cs or /we going high. 5. do not access device with cycle timing shorter than trc(twc) for continuous periods > 20us. 6. in case page address is over 3ns, write to the invalid address can occur. page write cycle (address controlled, /zz=v ih ) a4~a20 /cs /ub, /lb /we data out tas(3) high-z data undefined data valid tdw tow twhz data in a0~a3 twc tpc tpc tpc tpc tpc tpc tpc high-z tdh data valid tdh tdw tdh tdw tdh tdw tdh tdw tdh tdw tdh tdw tdh tdw data valid data valid data valid data valid data valid data valid tmrc
FMP1617CCX cmos lpram revision 0.1 jun. 2006 10 low power modes 1. mode register set a0 a1 a2 a3 a4 a19 ~ a5 array refresh area half selection array on/off on /zz zz enable/disable 0 /zz enable/disable dpd disable (default) 1 deep power down enable 0 type a4 array on/off on /zz reduced memory size mode 1 partial array refresh mode (default) 0 type a3 note: if the register is written to enable the deep power down, the part will go into deep power down during the following time that /zz is driven low and there is no mrs update. when /zz is driven high, all of the register settings will return to default state for the part (i.e. full array refresh, deep power down disabled). note: the rms(reduced memory size) mode is enabled after /zz goes high and remains enabled after /zz goes high. to change to a different mode, the mode register will have to be rewritten. half selection (top / bottom) top 1 bottom (default) 0 type a2 array refresh area rfu 1 0 ? array 0 1 1 0 a1 ? array 1 full array (default) 0 type a0 2. mrs update address /cs /ub, /lb /we twc twr(4) tbw twp(1) tcw(2) tas(3) taw /zz tzzwe register write start register write complete register update complete the register update take place on the rising edge of /zz. once the register is updated, the next time /zz goes low, without an y updates to the register starting within the tzzwe max time of 1us, the part will refresh the array selected. the data bus is a don?t care when /zz is low during the register updates.
FMP1617CCX cmos lpram revision 0.1 jun. 2006 11 8mb 512kbx16 80000h-fffffh 1/2 10 1 4mb 256kbx16 c0000h-fffffh 1/4 11 1 16mb 1mbx16 00000h-fffffh full 00 x 8mb 512kbx16 00000h-7ffffh 1/2 10 0 4mb 256kbx16 00000h-3ffffh 1/4 11 0 density size address refresh section a1,a0 a2 partial array refresh mode (a3=0, a4=1) reduced memory size mode (a3=1, a4=1) 3. deep power down mode entry/exit 4. address information tzzmin tr a4 /cs /ub, /lb /we twc twr(4 ) tbw twp(1) tcw(2 ) tas(3) taw /zz tzzwe register write(dpd) deep power down start deep power down exit next cycle 8mb 512kbx16 80000h-fffffh 1/2 10 1 4mb 256kbx16 c0000h-fffffh 1/4 11 1 8mb 512kbx16 00000h-7ffffh 1/2 10 0 4mb 256kbx16 00000h-3ffffh 1/4 11 0 density size address refresh section a1,a0 a2 us - 10 low power mode time tzzmin us - 200 operation recovery time tr(deep power down mode only) us 1 0 zz low to write enable low tzzwe units max min description parameter
FMP1617CCX cmos lpram revision 0.1 jun. 2006 12 package dimension 48 ball fine pitch bga (0.75mm ball pitch) top view b c #a1 bottom view side view detail a unit : millimeters 0.08 - - y 0.30 0.25 0.20 e2 - 0.85 - e1 1.20 1.10 - e 0.40 0.35 0.30 d - 5.25 - c1 8.10 8.00 7.90 c - 3.75 - b1 6.10 6.00 5.90 b - 0.75 - a max typ min - d c e2 e e1 0.30 0.85/typ. 0.25/typ. y notes. 1. bump counts : 48(8row x 6column) 2. bump pitch : (x,y)=(0.75 x 0.75)(typ.) 3. all tolerance are +/-0.050 unless otherwise specified. 4. typ : typical 5. y is coplanarity : 0.08(max) b c b/2 b1 0.05 0.05 a1 index mark 6 5 4 3 2 1 a b c d c1/2 c1 e f g h a

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